1. Field of the Invention
The present invention relates to a multi-level circuit substrate having interlayer connection through a conductor filled between layers thereof, a method for manufacturing same and a method for adjusting a characteristic impedance therefor.
2. Description of the Related Art
Recently there has been an increasing demand for implementing high density mounting of semiconductor devices with increase in the need to enhance operation speed and improve performances for the computers. In the high end field of super-computers, etc., the ceramic substrate utilized in semiconductor device mounting is structured by two interconnect layers sandwiched between ground layers (or power source layers). This have realized reduction of cross talk and control of characteristic impedance together with high density mounting. For data transfer utilizing a high clock frequency, however, the adoption of such a structure cannot provide for sufficient effects to reduce cross talk and control characteristic impedance.
Under such a situation, in conventional there has been a technology disclosed in a publication of Japanese Patent Laid-open No. 206678/1993. In this technology, five or more shield connection members are provided for a multi-level substrate having a shield connection member around a signal connection member thereof. Due to this, the reduction of cross talk and stabilization of characteristic impedance are achieved at around interlayer connecting portions. However, such a structure requires many connection members for the interconnect substrate. Thus, there is insufficiency in compatibility with today""s high density mounting and increase in number of pins.
It is therefore an object of the present invention to provide, with high density and at low cost, signal-line connection members that are reduced in signal reflection due to a difference in characteristic impedance between the signal interconnect layer and the signal-line connection member, thereby realizing both characteristic impedance stability and high density mounting.
Another object of the invention is to reduce the size of a substrate structure required for characteristic impedance matching.
In order to achieve the objects, the present invention comprises: at least two interconnect layers oppositely placed to each other; an insulator provided between the interconnect layers; connection members provided penetrating through the insulator along an opposed direction of the interconnect layers and connecting between the interconnect layers; an intermediate connection layer sandwiched by the connection members at a center position of the connection members provided along the opposed direction of the interconnect layers and electrically connecting between one end and the other end of the connection members; a shield layer provided nearly on a same plane as the intermediate connection layer and placed spaced from around the intermediate connection layer; and wherein a condition of (Rxc2x7r)/(2xc2x7h)xe2x89xa6Lxe2x89xa6(5xc2x7Rxc2x7r)/h is satisfied, provided that a connection distance between the interconnect layers through the connection members and the intermediate connection layer is h, the connection members where considered generally as a circular cylinder has a diameter R, the intermediate connection layer where considered generally as circular has a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L.
The present invention, satisfied by this condition, can provide matching in characteristic impedance between the interconnect layers and the connection members to a degree of a signal reflectivity of less than 0.05.